High speed signaling circuits, i.e. circuits with switching times under one nanosecond, place severe demands upon the power distribution components of digital circuit boards, i.e. PC boards. Modern PC boards frequently have hundreds of output drivers changing signal levels simultaneously in response to a system clock. The drivers require large instantaneous currents to be delivered from a power supply to charge up the distributed capacitance of the interconnect signal lines. Large voltage drops can result in the power distribution network when the high switching currents are impeded by resistance or inductance. These drops can propagate throughout the power distribution network and, if severe enough, cause logic errors.
A conventional digital driver/receiver pair is shown in FIG. 1, comprising a driver chip 10 and a receiver chip 12, both connected to a power supply plane 18 and a ground plane 28 of a PC board, and communication via a signal output line 20 from driver chip 10 to receiver chip 12. Driver chip 10 includes a pair of transistors 14 and 16 connected in series between the power and ground planes 18 and 28, with transistor 14 being on when transistor 16 is off, and visa versa. In the steady state, when transistor 14 is on, signal line 20 is at a relatively low voltage level, and when transistor 16 is on, signal line 20 is at a relatively high voltage level, which levels can be sensed by an amplifier circuit 24 in receiver chip 12 and compared to a reference voltage V.sub.s to give either a logic low or logic high output V.sub.out. To switch states on signal line 20 and to send a new logic output to the receiver 12, current, represented here by arrows, must be switched from the power supply plane 18 to the signal output line 20. The signal current flows through signal line 20 to the receiver termination 22 and develops a voltage across the termination resistor 26 to ground. The ground return current flows through the ground plane 28 back towards driver chip 10. Box 30 represents a bypass capacitor somewhere on the PC board which is connected between lines 18 and 28. The circuit inside the box 30 is an equivalent circuit which depicts the bypass capacitor as an ideal capacitor 33 in series with a parasitic inductance 34. Bypass capacitor 30 provides a low impedance return flow path for the signal current so that the signal current does not have to flow through the power supply. The current returns via the bypass capacitor and power supply plane 18 to the switching output device 10, completing the circuit.
There are several problems with the conventional driver circuit just described. One problem already alluded to has to do with power supply noise in the form of voltage drops introduced when high switching currents are impeded by resistance or inductance. The relatively large physical distance between the switching drivers 10 and the power supply bypass capacitor 30 causes increased power supply inductance 32 and 34, which restricts the flow of current to the drivers 10, increasing the noise. Mutual inductance present in the power supply source path 18 causes adjacent signal line coupling through the driver chip 10 and through the power supply bypass capacitor 30, which is located far away from the switch devices 10. Bypass capacitors 30 are ineffective at maintaining constant voltage at fast switching speeds due to the series inductance 34 inherent in any physical capacitor. Power supply noise voltages that have not been properly bypassed propagate throughout the entire PC board and add in amplitude at any given time and location, increasing PC board noise significantly.
Another problem with conventional driver circuits has to do with the signal propagation time through the ground return path 28. The relatively large physical distance between the drivers 10 and the bypass capacitor 30 results in a long return path and a correspondingly long propagation time. A signal traveling in a 60 cm (2 ft) circuit board at half to two-thirds of light speed propagates through the signal line in two to four nanoseconds, then returns through the ground path for about four nanoseconds more. This six to eight nanosecond signal delay is comparable in size to the ten nanosecond rise times for signal pulses of TTL and CMOS circuits. A signal pulse is such, and not spurious noises, only because it is larger than its own propagation delay time. Unfortunately, the long return paths of conventional driver circuits are incompatible with the one to three nanosecond pulse rise times of ECL circuits and the 0.2 nanosecond second pulse rise times of GaAs circuit technologies. It is an object of the present invention to provide a digital switching circuit, i.e. a driver/receiver pair, which minimizes the voltage drops in the power distribution methods that occur during switching.
It is another object of the present invention to provide a digital switching circuit with a significantly reduced signal propagation delay time.